1. Field of the Invention
The present invention relates to a semiconductor storage device. In particular, the invention relates to a semiconductor storage device having a sense amplifier.
2. Description of Related Art
FIG. 4 is a circuit diagram showing a sense amplifier of a conventional semiconductor storage device. As shown in FIG. 4, the sense amplifier SA is connected to bit lines BL and /BL. The sense amplifier SA includes P-type MOS transistors PT1 and PT2 and N-type MOS transistors NT1 and NT2. A series connection of the P-type MOS transistor PT1 and the N-type MOS transistor NT1 is provided between nodes SP and SN. A series connection of the P-type MOS transistor PT2 and the N-type MOS transistor NT2 is also provided between the nodes SP and SN. The gates of the P-type MOS transistor PT1 and the N-type MOS transistor NT1 are connected to the bit line /BL and a node N2 that is located between the P-type MOS transistor PT2 and the N-type MOS transistor NT2. The gates of the P-type MOS transistor PT2 and the N-type MOS transistor NT2 are connected to the bit line BL and a node N1 that is located between the P-type MOS transistor PT1 and the N-type MOS transistor NT1.
Next, the operation of this sense amplifier SA will be described below with reference to a timing chart of FIG. 5. FIG. 5 shows a case where the pre-charging potential is (Vdd+Vss)/2, that is, the middle potential between a power source potential Vdd and a ground potential Vss and information stored in the memory cell is read out and the potential of the bit line BL thereby becomes higher than that of the bit line /BL by .DELTA.V. In a state that information stored in the memory cell has been read out to cause a potential difference .DELTA.V between the bit lines BL and /BL, the potential of the node SN is decreased from (Vdd+Vss)/2 to the ground potential Vss. As a result, the N-type MOS transistors NT1 and NT2 are turned on. Since the potential of the bit line BL is higher than that of the bit line /BL, a current flowing through the N-type MOS transistor NT2 is larger that a current flowing through the N-type MOS transistor NT1. Therefore, the potential of the bit line /BL decreases toward the ground potential Vss and the current flowing through the N-type MOS transistor NT1 decreases. Therefore, the potential of the bit line BL decreases slightly and the potential difference between the bit lines BL and /BL increases.
Then, the potential of the node SP is increased from (Vdd+Vss)/2 to the power source potential Vdd. As a result, since the potential of the bit line /BL is lower than that of the bit line BL, a larger current flows through the P-type MOS transistor PT1 than the P-type MOS transistor PT2. Therefore, the potential of the bit line BL increases toward the power source potential Vdd. As the potential of the bit line BL increases, the current flowing through the P-type MOS transistor PT2 decreases. As a result, the potential difference between the bit lines BL and /BL is amplified to Vdd-Vss.
For a differential sense amplifier shown in FIG. 4 to perform a normal amplifying operation, the potential difference .DELTA.V that occurs when information is read out from the memory cell should be larger than a certain value. Unless the memory cell capacitor has a large capacitance value, the potential difference .DELTA.V does not become larger than the certain value. Therefore, the size of the memory call cannot be reduced unduly. This is one factor of preventing reduction of the chip area.